Analog Dialogue, Volume 44, Number 3

Analog Dialogue Volume 44 Number 4. 3. Two Ways to Measure Temperature. Using Thermocouples Feature. Simplicity, Accuracy, and Flexibility. By Matthew.
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From an implementation standpoint, many different error sources need to be reduced or eliminated to achieve this performance level.

ADALM1000 SMU Training Topic 9: Power and Power Factor in AC Circuits

The geometry of the traces from the analog and clock inputs of each ADC needs to be matched to ensure that the propagation delays are within their budgeted levels. While the clock function is relatively simple, it can also introduce errors that threaten these performance Analog Dialogue Volume 39 Number 2 Differences in power-supply-level behavior can create the need to use tight-tolerance supplies, such as linear regulators mounted in close proximity to the ADCs.

Also, temperature-related behavior creates the need to manage the mechanical design to ensure tight temperature matching of the ADCs. The ADCs themselves may need to be screened for one or all of the following: Obviously screening four individual ADCs for tight tolerances in all their key parameters would be very difficult and costly!

Such added complexity and increased risk must be weighed against the development and component cost goals of a system design. Advanced technologies, such as silicon-germanium RSECL reduced-swing ECL , can offer orders-of-magnitude improvement in rise-, fall-, and propagation-delay times when compared with those of their contemporary ECL counterparts. Depending on the input frequency, manual length trims may be used to overcome aperture delay errors as well. AD wide-band image-spur performance. Thus, when system designs require sample rates that are higher than commercially-available individual ADCs can handle, time interleaving is worth considering.

If to bit performance is required over the entire Nyquist band, integrated solutions such as the AD and AD provide the benefits of time interleaving by successfully managing the difficulties associated with very tight channel-matching requirements. Time Interleaving We have summarized here two techniques for achieving performance beyond the capability of currently available single ADCs. The fact that such standard products are available—with design problems solved and standard specifications provided—may be sufficient for many readers. However, the following comments are for the benefit of users who may wish to further investigate the possibilities of these areas of performance using available standard single or multichannel uncommitted ADCs.

A common metric that can be used to compare topologies is SNR. The clocks for the four ADCs in the averaging circuit can be derived from a resistive splitter, a magnetic splitter, or a simple 1: In some cases, four additional flip-flops might be used to buffer the timing signal so as to maintain tight timing. In order to achieve the desired 6 dB SNR improvement, the time-interleaving approach is likely to employ a digital filter that requires real-time multipliers and adders or a portion of processing time if available in the system design.

The averaging approach only requires a real-time adder, resulting in a substantial reduction in digital logic. The effectiveness of each noise-reduction technique must be carefully considered as well. In particular, the level of noise correlation and bandwidth in each channel must be understood. As the channel-to - channel noise correlation increases, the averaging approach becomes less effective. In systems for which the dominant noise source is jitter or phase noise, the noisecorrelation risk can degrade the SNR improvement. Time interleaving essentially spreads the noise over four times the bandwidth, then filters out the unused MHz.

In this case, the wideband characteristics of the noise spectrum must be studied and understood. However, if the noise-energy distribution is more prominent within the 40 -MHz band of interest, the SNR improvement goal of 6 dB might not be attainable. Another important factor to consider when comparing these topologies is frequency planning.

Therefore, they are reduced or removed altogether by the digital noise filter. In addition, the image spurs discussed above also fall outside of the band of interest and are thus filtered. In multitone systems, some of the components also fall out of the band of interest, lowering the total harmonic distortion of the system. In conclusion, averaging offers a simpler approach to achieving 6 dB of noise improvement, but time interleaving offers several benefits that may warrant consideration when developing system architectures.

Ultrasound systems seeking higher definition sum up to ADC channels for better signature. Digital oscilloscope manufacturers have developed ways to time interleave ADCs to accommodate their high sample rate requirements. As ADCs become increasingly available in multichannel integrated-circuit quad- and octaltype packages to save power and space, multiple-channel system architectures are being developed using them to provide functions or performance not previously available.

High-Speed Design Techniques, ed. Walt Kester, Analog Devices, Inc. The authors would also like to thank Brad Brannon for his technical expertise and guidance in writing this article. A direct approach is to go right to the selection guides and parametric search engines, such as those available1 on the Analog Devices website. Is there a way to approach the task with greater understanding—and better results? Most ADC applications today can be classified into four broad market segments: A basic understanding of these, the three most popular ADC architectures—and their relationship to the market segments—is a useful supplement to the selection guides and search engines.

ADC architectures, applications, resolution, and sampling rates. The classification in Figure 1 shows in a general way how these application segments and the associated typical architectures relate to ADC resolution vertical axis and sampling rate horizontal axis. The dashed lines represent the approximate state of t he ar t in mid - Even t hough t he var ious architectures have specifications with a good deal of overlap, the applications themselves are key to choosing the specific architecture required.

Successive-Approximation ADCs for Data Acquisition The successive-approximation ADC is by far the most popular architecture for data - acquisition applications, especially when multiple channels require input multiplexing. The architecture was first utilized in experimental pulse-code-modulation PCM Analog Dialogue Volume 39 Number 2 The basic successive-approximation architecture is shown in Figure 2. The comparator determines whether the SHA output is greater or less than the DAC output, and the result the most-significant bit MSB of the conversion is stored in the successive-approximation register SAR as a 1 or a 0.

The result 1 or 0 is stored in the register, and the process continues until all of the bit values have been determined. The acronym, SAR, which actually stands for successive-approximation register —the logic block that controls the conversion process—is universally understood as an abbreviated name for the entire architecture. The basic algorithm used in the successive-approximation ADC conversion process can be traced back to the s.

It is related to the solution of a useful mathematical puzzle—the determination of an unknown weight by a minimal sequence of weighing operations Reference 1. In this problem, as stated, the object is to determine the least number of weights which would serve to weigh an integral number of pounds from 1 lb. One solution put forth by the mathematician Tartaglia in , was to use the binary series of weights 1 lb. The proposed weighing algorithm is the same one that is used in modern successive-approximation ADCs. It should be noted that this solution will actually measure unknown weights up to 63 lbs.

TEST X switched in and out under control of autocalibration routines—to achieve high accuracy and linearity without the need for thinfilm laser trimming. Therefore, input multiplexing can be added to the basic SAR ADC function relatively straightforwardly, thus allowing the integration of a complete data-acquisition system on a single chip. Additional digital functions are also easy to add to SAR-based ADCs, so features such as multiplexer sequencing, autocalibration circuitry, and more are becoming common. The sequencer allows automatic conversion of the selected channels, or channels can be addressed individually if desired.

Data is transferred via the serial port. Successive-approximation ADC algorithm using balance scale and binary weights. However, the process of depositing and trimming thin-film resistors adds cost, and the thin-film resistor values may be affected after the device is subjected to the mechanical stresses of packaging.

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The principal advantage of the switched-capacitor DAC is that the accuracy and linearity are primarily determined by high-accuracy photolithography, which establishes the capacitor plate area, hence the capacitance and the degree of matching. High resolution, together with on- chip programmable -gain amplifiers PGAs , allows the small output voltages of sensors—such as weigh scales and thermocouples—to be digitized directly.

Proper selection of sampling rate and digital filter bandwidth also yields excellent rejection of Hz and Hz power-line frequencies. However, because digital filters then a rarity were Analog Dialogue Volume 39 Number 2 an integral part of the architecture, practical IC implementations did not appear until the late s, when signal processing in digital CMOS became widely available. In Figure 6B, the sampling frequency has been increased by a factor, K, the oversampling ratio , but the input signal bandwidth is unchanged.

The quantization noise falling outside the signal bandwidth is then removed with a digital filter. The output data rate can now be reduced decimated back to the original sampling rate, f S. The output of the modulator is a 1-bit stream of data. Because of negative feedback around the integrator, the average value of the signal at B must equal V IN.

If V IN is zero i. As the input signal goes more positive, the number of 1s increases, and the number of 0s decreases. Likewise, as the input signal goes more negative, the number of 1s decreases, and the number of 0s increases. The ratio of the 1s in the output stream to the total number of samples in the same interval—the ones density—must therefore be proportional to the dc value of the input. The modulator also accomplishes the noise-shaping function by acting as a low-pass filter for the signal and a high-pass filter for the quantization noise.

However, the digital filter does introduce inherent pipeline delay, which definitely must be considered in multiplexed and servo applications. Several output clock cycles are generally required for this settling. Increasing the number of integrators in the modulator similar to adding poles to a filter provides more noise shaping at the expense of a more complex design—as shown in Figure 8 for a second-order 1-bit modulator.

Note the improvement in the noise shaping characteristic compared to a first-order modulator. Higher-order modulators greater than third order are difficult to stabilize and present significant design challenges. While integrating architectures dual - slope, triple - slope, etc. These converters offer excellent power-line common-mode rejection and resolutions up to 24 bits as well as digital conveniences such as on- chip calibration. Many have programmable-gain amplifiers PGAs , which allow small signals from bridge - and thermocouple transducers to be directly digitized without the need for additional external signal conditioning circuits and in-amps.

Figure 9 shows a simplified diagram of a precision load cell. This particular load cell produces mV full-scale output voltage for a load of 2 kg with 5-V excitation. The diagram shows the bridge resistance values for a 2-kg load.

Analog Dialogue, Volume 45, Number 3

The output voltage for any given load is directly proportional to the excitation voltage, i. Evaluation boards and software can greatly assist in this process. Nevertheless, there are still many instrumentation and sensor signal- conditioning applications that can be efficiently solved with a traditional in-amp for signal amplification and common-mode rejection followed by a multiplexer and a SAR ADC.

In addition, the ease of adding digital functions to a CMOS-based converter makes features such as digital-filter programmability practical with only small increases in overall die area, power, and cost. Digital techniques for voiceband audio began in the early days of PCM telecommunications applications in the s. For more discussion on input-referred noise and noise-free code resolution see Further Reading 1.

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Ratiometric operation eliminates the need for a precision voltage reference. A traditional approach to digitizing this low-level output would be to use an instrumentation amplifier to provide the necessary gain to drive a conventional SAR ADC of bit to bit resolution. Appropriate filtering circuitry is needed due to the noise of the auto-zero in-amp.

Except for this small region, the applications considered high speed are most often served by a pipelined ADC. Although low-resolution flash converters remain an important building block for the pipelined ADC, they are rarely used by themselves, except at extremely high sampling rates—generally greater than 1 GHz or 2 GHz—requiring resolutions no greater than 6 bits to 8 bits.

Also requiring highspeed converters are video, radar, communications IF sampling, software radio, base stations, set-top boxes, etc. The pipelined ADC has its origins in the subranging architecture, first used in the s. A block diagram of a simple 6 -bit, two -stage subranging ADC is shown in Figure Residue waveform at input of second-stage SADC.

This waveform is typical for a low-frequency ramp signal applied to the analog input of the ADC. In order for there to be no missing codes, the residue waveform must not exceed the input range of the second-stage ADC, as shown in the ideal case of Figure 12A. The ADC output under such conditions might appear as in Figure At this point it is worth noting that there is no particular requirement—other than certain design issues beyond the scope of this discussion—for an equal number of bits per stage in the subranging architecture.

In addition, there can be more than two stages. Nevertheless, the architecture as shown in Figure 11 is limited to approximately 8-bit resolution unless some form of error correction is added. The error-corrected subranging ADC architecture appeared in the mids as an efficient means to achieve higher resolutions, while still utilizing the basic subranging architecture. The extra range in the second-stage ADC allows the residue waveform to deviate from its ideal value—provided it does not exceed the range of the second-stage ADC.

A basic 6-bit subranging ADC with error correction is shown in Figure 14, with the second-stage resolution increased to 4 bits, rather than the original 3 bits. The input SHA remains in the hold mode during the time required for the following events to occur: After the digital data passes through the error correction logic and output registers, it is ready for use; and the converter is ready for another sampling-clock input.

This latency may or may not be a problem, depending upon the application.

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When to Use a Double Transformer Configuration. Is No Noise Good Noise? Measuring small differential voltages in the presence of large common-mode voltages.

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