Embedded DSP Processor Design: Application Specific Instruction Set Processors (Systems on Silicon)

Embedded DSP Processor Design: Application Specific Instruction Set Processors (Systems on Silicon) [Dake Liu] on leondumoulin.nl *FREE* shipping on .
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Photography as Cultural Diplomacy by Kennedy, Liam, open-source web framework, with integrated support for unit, functional, and integration testing. Constitutional Law by Steven L. Application Specific Instruction Set Processors Systems on Silicon by Dake Liu, pdf, epub, mobi, fb2, djvu, lit, txt, rtf, doc, docx, chm, htmlz, lrf, azw, azw3, kindle, ebook, torrent, downloads. You are commenting using your WordPress. You are commenting using your Twitter account. A CATHEDRAL I1 processor contains a microcoded controller with powerful branching capabilities and a data path composed of multiple software-controlled modules called "execution units" EXU's , which are connected via a dedicated bus network [l].

Most EXU's have local register files at their data inputs. All EXU's are parametrizable e. The input to the compiler is a behavioral description of the DSP system in the applicative language Silage [ These tasks are defined in more detail in Section In the EXU binding process we distinguish three subtasks. For every Silage operation, the required EXU-types are determined first. This subtask is called EXU-type selection. For example, to implement a multiplication either an ALU or a parallel multiplier can be selected.

For every EXUtype, the required number of instances is determined next. This is called EXU allocation. For given type selections and allocations, specific EXU instances are finally bound to the Silage operations. This third subtask is termed EXU assignment. By iteratively refining the type selection and allocation, the designer can evaluate alternatives and optimize the architecture.

The basic entity in the language is the RT statement. With respect to timing, RT's are atomic2 operations since they each consume 1 machine cycle. The RT language contains a mixture of applicative signal flow and procedural control flow elements. The control-flow part is restricted to nested FOR-loops.

Application-specific instruction set processor

A loop is interpreted as a procedural iterator, i. The body of a loop is fully applicative, i. A typical statement in the RT language is shown in the following: The internal pipelining of the controller can be specified by means of simple parameters. A data path may be composed of arbitrary combinational building blocks, separated by registers. Communication between entities in the data path may occur either by means of dedicated connections or through buses.

Currently, a number of foreground register types register jiles, pipeline registers, and 1-b wide status latches to transfer signal flags to the controller and background register types RAM and ROM are supported. An essential property of a foreground register in our model is that it cannot contain more than one indexed version of a signal at a time, within a FOR-loop. The latter is required because the register file access is directly controlled by the microcoded controller, which repeats its instruction sequence every loop-iteration.

It is up to the scheduler to take these storage constraints into account. To be able to do so, the register information in the RT input language is essential. Note that the model can be extended to support delay lines of a given length. This will, however, not be discussed in this paper. The following tasks are performed by the microcode compiler. Generalized multiple-branching controller model. The minimal number of pipeline stages is indicated, but extra stages may be added. In practice, a program counter with incrementer will often be incorporated.

As a result, to each RT an integer time potential is attached. Time potentials differ from machine cycle numbers in that they discard the repetition, caused by FOR-loops. The basic scheduling technique is introduced in Section I11 of this paper. An original and important optimization of the control flow, embedded in the RT language, is achieved by allowing overlaps in time between successive FOR-loop iterations. This technique, called loop folding, is presented in Section V.

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Special attention is paid to register file dimensioning in the presence of loop constructs and conditions. The software techniques for this task are beyond the scope of this paper. The reader is referred to [9]. These artificial instances are called formal EXU instances. BEGIN 8 8 8 out: Their use will become more clear in Section IV. Therefore, the resulting schedule will only be valid when a contention-free bus network is available. This property is crucial to optimize the loop control-flow. In order to reduce the complexity of the scheduling problem for nested FOR-loops, loops are scheduled hierarchically, starting at the deepest level of nesting.

In this section, it is assumed that the scheduler is not allowed to change the con- This so-called data precedence constraint can be repretrol-flow information in the RT description, i. Data precedence graph of biquad filter, derived from the RT-code of Table In such cases, only precedences between groups are shown. In such case, a larger delay value may be required, which depends on the controller pipelining. Therefore, a data precedence occurs from RT in the current loop iteration to RT in the next iteration. In order to describe this kind of precedences, the following definition is introduced.

Given a FOR-loop with counter i and step length4 si. Different loop organizations of the same algorithm may lead to different looping degrees. Higher degrees do not occur in this example. Observe that precedence graphs may now become cyclic. However, cycles composed of precedences of degree 0 only are not allowed.

This is verified with the help of a dedicated tautology checking procedure. First the following theorem is given. Theorem 1 Constraint Projection: Proofi It suffices to state that the following conditions have to be met by the scheduler. If the production and consumption occur in different loop iterations i. Hence, 1 can be transformed from the absolute time axis to the time potential axis as follows: For any two versions of a signal, based on the procedural nature of the loop, it is possible to distinguish the old from the new version.

The scheduler must assure that the old version is consumed before the new one is produced. The determination of A p is the subject of Section O The obtained zeroth degree precedences are termed the forward and backward projections of the original precedence. The backward projection is only considered for precedence constraints via a foreground register. The precedence graph obtained after replacing the original precedences by their projections, is termed the projected precedence graph.

In general, this is a cyclic graph, containing only zeroth-degree precedences with Ap-dependent a r c weights. These arc weights may be nonpositive.

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A necessary condition for the existence of a schedule is that the realizability criterion [6] for cyclic graphs is satisfied, i. Application of the realizability criterion to all cycles in the graph derives a set of linear inequality constraints in Ap, which can be solved to determine theoretical lower and upper bounds on Ap.


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In practice, the minimal Ap-value is usually higher than this lower bound, due to the occurrence of additional conjlict constraints. The following projections always have Ap-independent weights: Note that one of both projections of a precedence constraint may sometimes be redundant such that it can be omitted. A few examples, demonstrating the use of the projection theorem are shown in Fig. It can be verified that the forward projection becomes redundant for this Apvalue. The bottom figure shows the projection of a precedence modeling a conditional dependency in a decision making application.

The large delay value 3 is the result of the internal controller pipelining. In this case, neither of the projections is redundant. As shown by this example, nonredundant negative weights are in practice only caused by conditional dependencies in decision making algorithms. Without loss of generality we can set the lowest time potential within the Fig. Examples demonstrating the constraint projection theorem. In general, scheduling is an NP-complete problem, for which heuristic techniques are required [2], [7].

The basic list scheduling algorithm requires an acyclic precedence graph with strictly positive arc-weights only: Algorithm I List Scheduling 1 p: Usually the scheduling priority of an RT Step 2. In this way, a global search in the data precedence graph is combined with a local heuristic selection criterion to take into account the resource conflict constraints which cause N P completeness. A few special measures can easily be added to the described technique, in order to take into account precedences with zero weight as well [ As described in Section A summary of this approach is given below; for a complete description we refer to , [ l l].

First of all, a lower-bound approximation Apestof the schedule length is computed, and with this value the precedence graph is projected c. This projected graph is scheduled while discarding all arcs with a negative weight. Next the schedule is iteratively refined to take into account the negative weights. In every core iteration step, certain operations in the schedule are delayed with respect to the previous solution, in an attempt to satisfy the arcs with negative weights.

If the resulting schedule, however, violates the estimated schedule length Apest,this estimate is increased and the process is repeated. It is shown that the algorithmic complexity of the EXU assignment process is dependent on the underlying architectural model. Most published approaches rely on an architectural model which allows decoupling of the assignment decisions for the individual operations. As a consequence, to each individual RT both a source EXU for fetching and modifying source data and a destination EXU for storing the result have to be assigned.

The FACET system contains an assignment algorithm of similar generality, based on clique-partirioning techniques [29]. Graph coloring and clique partitioning are equivalent problems. In other words, the scheduling and assignment tasks are decoupled, which is not conducive to optimality. In ATOMICS, scheduling and assignment are performed simultaneously, by calling a graph coloring procedure during the list scheduling step.

This modification deals with the treatment of conflict constraints at every time potential. In this case, the assignment must satisfy the condition that the corresponding formal EXU instances, referenced in these RT statements, are not merged into the same EXU instance in the data path. Such a condition is termed an assignment constraint. A set of assignment constraints can be represented as arcs in an undirected graph, called an assignment graph, the vertices of which correspond to the formal EXU instances.

This principle is illustrated for part of the biquad filter example in Fig. For example, assignment graph a in Fig. This leads to the following algorithm for EXU-assignment. Example demonstrating the construction and realizability of assignment graphs. In the course of the scheduling algorithm, no final assignment decisions are made: The final assignment is determined afterwards by selecting one particular coloring solution to the final assignment graphs. All existing solutions are equivalent in terms of the machine cycle count. They might, however, differ in various other aspects, such as the interconnect cost.

Note, however, that the cost of, e. The described vertex coloring problem is NP-complete [8]. The resolution index [ is a modified critical path measure. The smaller the resolution index, the more urgent is the RT. The growth of the vertexcolorable assignment graph is shown on the right. In case of the first loop, this is an empty graph.

If allocations are specified for several EXU-types simultaneously, a separate assignment graph must be constructed per EXU-type, each of which needs to be colorable. The application of Algorithm 2 to the biquad filter In the previous sections, it was assumed that the organization of FOR-loops in the RT-input description could not be changed by the scheduler. In this section, the concept of loopfolding is introduced [lo], which allows optimization of the given loop organization during scheduling. In this way, overlaps can be introduced between the execution times of successive loop iterations.

This reduces the number of time potentials covered by the loop. Especially in the case of nested loops, this may lead to important savings on the global machine cycle count. The folded schedule Fig. When applied to the implicit time loop in which the DSP system is embedded, loop folding may increase the number of sample periods between the supply of an input signal and the associated output. This effect is, however, compensated by the achieved reduction of the cycle count, which allows an increase in the sample frequency.

In the case of hierarchically nested loops, folding of one loop may require modijications of the initialization and termination code at the next higher level of hierarchy see Section V The loop folding technique allows exploitation of the algorithmic concurrency through pipelining. Every iteration of a FOR-loop represents a trace of operations, acting on successive versions of signals e. This corresponds to a pipeline.

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Related Work In general scheduling theory, the subject of loop optimization seems to be virtually untouched [ Although loop optimization is gaining attention in parallel compiler design see e. In the domain of high-level synthesis, approaches towards loop optimization in scheduling have been described in [26], [20], [5], [22].


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The first three systems are restricted to optimizing the implicit time loop of the DSP algorithm. During their execution, repetitive programs, however, spend most of their time in the inner loops. Consequently, any loop optimization technique should concentrate on inner loops.

HAL [22] can optimize nested loops but requires specification of the pipelining level for each loop in advance.

Embedded DSP Processor Design, : Application Specific by Dake Liu

A number of systems allow expansion or unrolling of FOR-loops before scheduling. Although it may produce time-efficient schedules as well, this approach often results in an explosion of microcode, and hence, in a waste of controller area. The so-desired repetitivity is sacrificed, making a successful reintroduction of the loop control-flow in the resulting schedule unlikely. In the Saw-system, manual loop transformations are supported at the same level.

Spaid uses a retiming algorithm to pipeline digital filter flow-graphs. We believe these approaches to be less accurate because the correct folding is largely dependent on constraints on the hardware resource utilization, which are only exactly known at the RT level. Iterative Folding of a Single Loop In this section, we present a technique to fold a single FOR-loop, without initialization or termination code and with an injinite number of loop iterations e. The case of nested loops is addressed in Section V Thefolding index of an RT is defined as follows.

Dejinition 2 Folding Index: The folding index 4 of an RT in a certain loop organization is the integer number of loop iterations over which the RT has been moved with respect to the original loop organization. Loop folding affects the indexed signal names occurring in the RT description: Loop folding does not change the topology of the data precedence graph, but it affects the looping degrees of individual precedences. Since looping degrees cannot be negative, the following restrictions should be taken into account during folding.

Based on an evaluation of this schedule, the proposed folding may be adjusted in a next iteration step, in order to further reduce the Ap-value. Each time the looping degrees are updated according to Corollary 1. In the overall approach, three nested iteration levels occur: Owing to the properties of our folding heuristics see below , only two levels of nesting are encountered in practice.